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KS0164 multimedia audio 1 / 19 overview the KS0164 wavetable synthesizer chip represents the state-of-the-art in multimedia audio technology. the KS0164 combines a high-quality 32-voice wavetable synthesizer, a powerful 16-bit cpu and an mpu-401 compatibility into a single chip. the audio performance of a typical KS0164 system compares favorably to the best multimedia audio solutions available today, but at a fraction of the cost. a typical KS0164 system provides 32 voices of 16-bit, 44.1 khz sample rate wavetable synthesis, mpu-401 compatibility, general midi, gs and mt-32 compatibility. with KS0164, a complete wavetable synthesizer may be implemented with as few as three ics. both serial and parallel midi interfaces are provided. 100 pqfp ordering information device package temperature range KS0164 100-qfp 0 ~+70 c applications multimedia audio products musical synthesizers video game sound systems related products ks0174-1m 1mb sample rom ks0174-2m 2mb sample rom ks0174-4m 4mb sample rom kf353/d/s dual operational amplifier features high-quality 32-voice wavetable synthesizer general midi compliant three serial output channels for addition of optional audio effects processor supports all common cdp d/a formats supports up to 24mbytes of sample memory supports 8-bit, 16-bit and compressed samples directly supports rom, sram and dram hardware-based roland mpu-401 emulation 16-bit embedded cpu minimizes host pc overhead integrated sram for embedded cpu integrated midi uart software-controlled sleep mode sequoia pegasus synthesizer firmware 100 pin pqfp package
KS0164 multimedia audio 2 / 19 block diagram application block diagram 16-bit embedded cpu ha[9:0] haenl hiorl hiowl hrst hdbenl bas[1:0] mpu401 emulation hd[7:0] midi uart memory i/f ras cas[2:0] we[1:0] md[15:0] ma[22:0] txd rxd addr[22:0] mpu-int uart-int sdat[2:0] lrclk bclk configuration registers data[15:0] msize[1:0] hint hrstpol datyp[1:0] host pc i/o interface 32-voice wavetable synthesizer isa bus sram cas3 ma[12:1] wdclk mtype csl
KS0164 multimedia audio 3 / 19 pin assignment - 100 pqfp KS0164 50 49 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31 44 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 ma11 ma12 gnd v dd ma13 ma14 ma15 ma16 ma17 ma18 ma19 ma20 ma2 ma1 md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 md5 md4 md3 v dd gnd md2 md1 md0 ma21 ma22 we0* we1* ras* cas1* cas0* cas2* clksel gnd v dd extclk hiow* hior* haen* osco osci hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 hdben* ha1 ha0 samsung ma0 mclk ha3 ha2 ha4 ha5 ha6 ha7 ha8 ha9 hint hrst test mtype msize1 msize0 datype1 datype0 bas1 bas0 csl* hrstpol gnd v dd txd rxd lrclk wdclk sdat2 sdat1 sdat0 bclk
KS0164 multimedia audio 4 / 19 pin assignment (continued) pin # pin name pin # pin name pin # pin name pin # pin name 1 hrst 26 hd0 51 ma11 76 md4 2 hint 27 clksel 52 ma10 77 md3 3 ha9 28 extclk 53 ma9 78 md2 4 ha8 29 osci 54 ma8 79 md1 5 ha7 30 osco 55 ma7 80 md0 6 ha6 31 mclk 56 ma6 81 test 7 ha5 32 cas2* 57 ma5 82 mtype 8 ha4 33 cas1* 58 ma4 83 msize1 9 ha3 34 cas0* 59 ma3 84 msize0 10 ha2 35 ras* 60 ma2 85 datype1 11 ha1 36 we1* 61 ma1 86 datype0 12 ha0 37 we0* 62 ma0 87 bas1 13 hior* 38 ma22 63 md15 88 bas0 14 hiow* 39 ma21 64 md14 89 csl* 15 hdben* 40 gnd 65 gnd 90 hrstpol 16 haen* 41 v dd 66 v dd 91 gnd 17 gnd 42 ma20 67 md13 92 v dd 18 v dd 43 ma19 68 md12 93 txd 19 hd7 44 ma18 69 md11 94 rxd 20 hd6 45 ma17 70 md10 95 lrclk 21 hd5 46 ma16 71 md9 96 wdclk 22 hd4 47 ma15 72 md8 97 sdat2 23 hd3 48 ma14 73 md7 98 sdat1 24 hd2 49 ma13 74 md6 99 sdat0 25 hd1 50 ma12 75 md5 100 bclk
KS0164 multimedia audio 5 / 19 pin description pin name pin # type description host pc interface ha9-0 3-12 i host address bits 9-0. these are the low 10 bits of the host pc address bus, which are decoded to control access the mpu-401. for ibm pc application, these pins should be connected directly to a[9:0]. alternatively, these pins may be tied to gnd, and a fully qualified chip select signal may be connected to the csl* pin instead. haen* 16 i host address enable. this is the host pc address decode enable. when low, this signal enables the on-chip address decoder to decode ha[9:0], according to the base address selected by the bas[1:0] signals. in this mode, the csl* may be used instead. in this mode, only ha[3:0] will be decoded. for ibm-pc applications, this pin should be connected directly to aen*. bas[1:0] 87,88 i base address select. these signals select the base address for the mpu-401 emulation as follows: 00b => 320-321h 01b => 330-331h 10b => 340-341h 11b => 350-351h csl* 89 i chip select. for use at non-standard i/o addresses, or in applications where a chip select signal is available, haen* may be tied high, and the external chip select connected to csl* instead. in this mode, only ha[3:0] are decoded on-chip. hd[7:0] 19-26 i/o buffered host pc data bus bits [0:7]. hior* 13 i host i/o read. this is the host pc i/o read enable. the chip will only drive the hd[7:0] bus when a valid address decode is present, as determined by the haen*, bas[1:0], and csl* signals, and hior* is low. hiow* 14 i host i/o write. this is the host pc i/o write strobe. data is written to internal registers on the rising edge of this signal. hrst 1 i host pc reset. the active polarity of this signal is determined by the hrstpol pin. for ibm pc application, this pin should be connected directly to the pc-bus rstdrv signal. for daughter card applications, connect this pin to the reset signal from the host board. hrstpol 90 i hrst polarity select. this signal selects the active polarity for the hrst signal. when this pin is tied low, hrst will be active low. hdben* 15 o host pc data bus buffer enable. this output controls the enable to the 74ls245 which buffers the host pc data bus. this pin is driven low any time the mpu-401 is addressed for an i/o access. hint 2 o host mpu-401 interrupt. this is a active high interrupt output from the mpu-401. it should be connected to one of the host irq lines, normally irq2.
KS0164 multimedia audio 6 / 19 pin name pin # type description memory interface ma[22:0] 38,39 42-62 o memory address bus bits [22:0]. this is the external memory address bus. when accessing static memory devices (rom/sram), these pins will contain a stable address throughout the entire memory cycle. when accessing dynamic memory, pins ma[11:0] will contain the multiplexed dram address. md[15:0] 63,64, 67-80 i/o memory data bus bit [15:0]. this is the external memory data bus. we1* 36 o memory upper byte write enable. when this signal is low during an external memory access, it indicates that data bits md[15:8] should be written to the addressed memory device. we0* 37 o memory lower byte write enable. when this signal is low during an external memory access, it indicates that data bits md[7:0] should be written to the addressed memory device. ras* 35 o dynamic memory row address strobe. this signal is the row address strobe for all external dram. when a dram device is addressed, this signal will be driven low shortly after the row address has been placed on ma[11:0]. it will also be driven low during rom/sram cycles to provide cas-before-ras refresh for any dram devices in the system. cas*[2:0] 32-34 o dynamic memory column address strobes/static memory chip selects [2:0]. up to three memory devices are supported. device 0 must be a 16- bit wide rom. devices 1 and 2 may be either static or dram, although both must be the same type. the configuration of devices 1 and 2 is determined by the msize and mtype[1:0] signals. when a dram device is addressed, one of these signals will be driven low shortly after the column address has been placed on ma0-11. it will also be driven low during static memory cycles to provide cas-before-ras refresh for any dram devices in the system. when a static device is addressed, one of these signals will be driven low shortly after the address has been placed on ma0-22. mtype 82 i memory type select. this signal selects the type of memory device to be connected to cas1* and/or cas2*. when tied low, static memory devices are selected. when tied high, dram is selected. msize[1:0] 83,84 i dynamic memory size select. if the mtype signal is tied high, these signals select the size of the dram devices connected to cas1* and/or cas2* as follows: 00b => 64k 01b => 256k 10b => 1m 11b => 4m mclk 31 o memory clock. cpu and synthesizer external memory accesses are 1:1 interleaved. this signal indicates which device currently has control of the memory bus. when low, the cpu has control of the memory bus, when high, the synthesizer has control of the memory bus.
KS0164 multimedia audio 7 / 19 pin name pin # type description d/a & effects processor interface sdat[2:0] 97-99 o d/a converter serial data [2:0]. these are the three serial data outputs from the synthesizer core. three outputs are provided so that one ?d ry ? channel, and two separate effects channels can be provided by an external audio effects processor. in a minimum configuration, with no effects external processor, sdat[0] would be connected to the data input of an external 16-bit stereo serial d/a converter, while sdat[2:1] would be left unconnected. bclk 100 o d/a converter bit clock. this is the bit clock for the external serial d/a converter for the synthesizer. lrclk 95 o d/a converter l/r clock. this is the l/r clock for the external serial d/a converter for the synthesizer. wdclk 96 o d/a converter word clock. this is the word clock for the external serial d/a converter for the synthesizer. datype[1:0] 85,86 i d/a converter serial data format select. these signals select the data format of the d/a devices as follows: 00b => 32-bit frame, i 2 s (1 bclk delay) 01b => 32-bit frame, (no delay) 10b => 64-bit frame, left justified 11b => 64-bit frame, right justified (japanese) clock input osci 29 i 16.9344 mhz oscillator buffer input. this input will normally be connected to one side of a 16.9344mhz crystal, with a 20pf capacitor to ground. if desired, an externally generated 16.9344mhz clock may be connected to this pin instead. note that due to internal analog circuitry, the chip may not behave reliably if this clock input is not close to the design frequency. osco* 30 o 16.9344 mhz oscillator buffer out. this input will normally be connected to one side of a 16.9344mhz crystal, with a 20pf capacitor to ground. if the osci pin is being driven by an externally generated clock, this pin should be left unconnected. extclk 28 i external clock input. this input may be used to make use of an externally generated clock in place of the on-chip oscillator. this clock may be of any frequency up to 33mhz. clksel 27 i external clock select. when this pin is low, the on-chip oscillator is disabled, and extclk is used as the clock source for all on-chip timing. when high, the on-chip oscillator is enabled. power and ground v dd 18,41,66,92 +5v digital power supply. gnd 17,40,65,91 gnd digital ground.
KS0164 multimedia audio 8 / 19 pin name pin # type description miscellaneous rxd 94 i midi receive data. this is the ttl-level serial input to the 31.25 kbaud midi uart. for normal midi communication, this pin must be driven by an external opto-isolator from the current-loop midi line. txd 93 o ttl midi transmit data. this is the ttl-level serial output from the 31.25 kbaud midi uart. for normal midi communication, this pin must drive an external voltage-to-current converter to drive the current-loop midi line. test 81 i manufacturing test pin. for normal operation, this pin must be tied to gnd. applying power to the device with this pin floating or tied to a logic high level may cause permanent damage to the device
KS0164 multimedia audio 9 / 19 general description the KS0164 is a highly integrated wavetable synthesizer chip, designed to be a part of a high- performance, low-cost multimedia audio systems. the chip contains a complete 32-voice, 16-bit, 44.1khz wavetable synthesizer, a high-performance 16-bit cpu, extensive compatibility with established standard audio interfaces, all necessary system glue logic and total software configurability. with its on- chip cpu, a KS0164-based synthesizer imposes absolutely minimal host cpu overhead. its hardware-based mpu-401 emulation completely eliminates the memory overhead, software compatibility and stability problems of tsr-based emulations. the following sections give a brief description of the major functional blocks of the KS0164. h ost pc i nterface all necessary isa bus interface logic is completely contained on-chip. this includes address decoding for the mpu-401 emulation, control signal interpretation, and optional data bus buffer control. all pc interface control logic operates completely asynchronously to the synthesizer/cpu logic. standard interfacing techniques are used to provide a highly compatible and reliable interface. the mpu-401 emulation can be decoded for any one of four standard address ranges, as selected by the bas[1:0] pins. in addition, a serial midi interface may be used, leaving the mpu-401 emulation inactive. this mode is particularly useful for stand- alone synthesizer modules and waveblaster-type daughter board applications. to better support non-pc-based applications, including stand-alone applications where no host cpu is available, the reset signal polarity is programmable via the hrstpol pin, to accommodate existing active high or active low reset signals. mpu-401 i nterface one of the two available interfaces for communicating midi data to/from the KS0164 is the on-chip mpu-401 emulation. this emulation provides the full hardware functionality of a real mpu-401. mpu-401 uart mode is fully supported, while a subset of the ?i ntelligent ? mode commands are also supported. the intelligent-mode support currently provided is adequate to support nearly all existing mpu-401 applications. midi uart i nterface the second of the two available interfaces for communicating midi data to/from the KS0164 is the on-chip of midi uart. this interface is always active, and works independently from the mpu-401 emulation, allowing the KS0164 to easily be used in stand-alone midi modules and waveblaster-type daughter board applications. e mbedded cpu in sharp contrast to most other low-cost multimedia audio solutions currently available, the KS0164 does not rely on the host pc processor or an external microcontroller to drive the wavetable synthesizer. rather, the KS0164 contains a high-performance purpose-built 16-bit cpu incorporating such advanced features as six different addressing modes, a hardware multiplier, a barrel shifter, and a peak execution rate of nearly 3 million instructions per second. in addition to providing optimal synthesizer audio quality, this reduces host pc cpu overhead. the considerable memory overhead, compatibility problems, and erratic audio quality associated with tsr-based solutions are also completely eliminated. s ynthesizer the synthesizer is a high-performance 32-voice, 16- bit wavetable synthesizer. while nearly all wavetable systems being offered today operate at sample rates ranging anywhere from 22-32khz, the KS0164 performs all sample processing at a full 44.1 khz. in addition, some other systems support only 12-bit samples. the KS0164, on the other hand, supports 8- and 16-bit linear samples, and 8- and 12-bit compressed samples. this allows nearly optimal tradeoffs between sample size and audio quality on a sample-by-sample basis in the design of the sample set, resulting in the best possible sound quality from a given total sample memory size.
KS0164 multimedia audio 10 / 19 general description (continued) the specification for the synthesizer are as follows: architecture: digital wavetable synthesizer voices: 32 polyphony: 32 notes maximum multi- timbral capability: up to 16 parts sample memory: up to 16 mwords of rom/sram/dram available sample sets: 2mx16-bits, 1mx16-bits, 512kx16-bits d/a converter: 16-bit linear serial converter, all common data formats supported sample playback rate: fixed @ 44.1 khz level and panning controls: separate 16-bit l&r volume controls for each voice filters: 2 separate 2-pole resonant digital filters for each voice data formats: 8- or 16-bit signed linear or 8- or 12-bit compressed envelopes: hardware envelopes for amplitude and filters effects: effects loop provided for dsp multiple effects processor firmware: sequoia development group pegasus synthesizer firmware compatibility: fully general-midi compliant roland mt-32 sound set compatible s ystem t iming a nd c ontrol all timing is derived from a 16.9344 mhz crystal oscillator, or an externally generated oscillator of any frequency up to 33 mhz. however, note that the internal midi uart baud rate is directly proportional to the system clock rate. at any crystal frequency other than 16.9344 mhz, the uart baud rate will not be correct. s ample m emory i nterface each memory access cycle consists of 3 cycles of the 16.9344 mhz master clock, or 177.15 nsec. this is adequate to allow use of 150 nsec rom, and 80 nsec dram. the memory interface supports a minimum of one and a maximum of three memory devices. in general the cpu will execute entirely out of rom, and most, if not all, synthesizer voices will also be playing primarily from rom, although entirely ram-based systems are also fully supported. rom memory accesses are exploited to allow dram refresh to occur simultaneously with rom accesses by executing cas-before-ras refresh cycles on all dram banks in parallel with all rom/sram accesses. for systems with rom-based samples, this scheme provides adequate refresh for all dram in the system. for a totally dram-based system, it is necessary to allocate one synthesizer voice to perform dram refresh. for a combined rom/dram system, as long as at least two voices are playing samples from rom at all times, adequate refresh will be provided automatically, otherwise one voice must be dedicated to providing dram refresh.
KS0164 multimedia audio 11 / 19 register description direct-addressed registers mpu-401 d ata r egister r ead /w rite a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+0 hmad d7 d6 d5 d4 d3 d2 d1 d0 d[7:0] mpu-401 a data. mpu-401 c ommand r egister w rite o nly a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+1 hmac c7 c6 c5 c4 c3 c2 c1 c0 c[7:0] mpu-401 a command. mpu-401 s tatus r egister r ead o nly a ddress m nemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 base+1 hmac rxrdy txrdy 1 1 1 1 1 1 rxrdy received data ready status 0 = received data is available in hmad 1 = received data is not available txrdy transmit data buffer ready status 0 = mpu-401 is ready to receive next data/command in hmad or hmac 1 = mpu-401 is not ready to receive next data/command
KS0164 multimedia audio 12 / 19 electrical specification absolute maximum ratings c haracteristics s ymbol m in m ax u nit supply voltage (measured to v ss ) v dd -0.5 +7.0 v input voltage (any pin) v in v ss -0.5 v dd +0.5 v ambient operating temperature range t opr 0 +70 c storage temperature range t stg -55 +150 c notes: 1. absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. functional operation under any of these conditions is not implied. dc electrical characteristics c haracteristics s ymbol m in t yp m ax u nit supply voltage (measured to gnd) v dd 4.75 5.0 5.25 v input high voltage v ih 2.2 - v dd +0.3 v input low voltage v il v ss -0.3 - 0.8 v digital output high voltage (i oh =400 m a) v oh 2.4 - - v digital output low voltage (i ol =3.2ma) v ol - - 0.45 v input leakage high current i ih -10 0 10 m a input leakage low current* i il -10 0 10 m a supply current i cc - 100 250 ma pull-up resistance** r up 40 - 250 k w test condition : v dd =5.0v, v ss =0v, f osc =16.9344mhz, t a =25 o c * for pins test, mtype, msiz[1:0], bas[1:0], hrstpol, hrst, datype[1:0] and csl ** all input pins except ones in *
KS0164 multimedia audio 13 / 19 electrical specification (continued) ac electrical characteristics c haracteristics s ymbol m in t yp m ax u nit memory cycle time t cyc - 177 - nsec memory address/control delay t dly - 15 - nsec memory read data setup time t rdsu 15 - - nsec memory read data hold time t rdh 0 - - nsec ras* active time t ras - 88 - nsec cas* active delay time t cdly - 29 - nsec cas* active time t cas - 59 - nsec row address setup time t rasu - 44 - nsec row address hold time t rah - 29 - nsec column address setup time t casu - 29 - nsec oscillator frequency f osc - - 16.9344 mhz test condition : v dd =5.0v, v ss =0v, f osc =16.9344mhz, t a =25 o c
KS0164 multimedia audio 14 / 19 rom/sram memory interface timing dram memory interface timing mclk ma[11:0] din dout ras* cas* cs, we* t dly t cyc t rdsu t rdh t ras t cdly t cas t dly mclk ma[11:0] din dout ras* cas* cs, we* t dly t cyc t rdsu t rdh t ras t cas t dly t rasu t rah t casu
KS0164 multimedia audio 16 / 19 audio board design & pcb layout guidelines 16 clocks 32-bit frame data formats left channel data 64-bit frame data formats b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b1 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 xx b15 b14 b13 b3 b2 b1 b0 xx xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx xx b15 b14 xx xx xx xx xx b0 xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx xx xx xx xx xx b15 b14 b13 b3 b2 b1 b0 xx xx b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 bclk (1.411mhz) 16 clocks left channel data bclk (2.822mhz) 32 clocks 32 clocks right channel data right channel data lrclk (44.1khz) lrclk (44.1khz) 32-bit i 2 s (datype[1:0] = 00) 32-bit nodelay (datype[1:0] = 01) 64-bit lj (datype[1:0] = 10) 64-bit rj (datype[1:0] = 11)
KS0164 multimedia audio 17 / 19 overview proper analog circuit design and pcb layout are essential to achieving optimum audio performance, as well as acceptable emi (fcc/vde) characteristics from pc audio boards. this document outlines the basic guidelines that should be followed to ensure acceptable performance in these critical areas. as a reference, please refer to the evaluation board schematics and pcb layout. design overview in order to achieve optimum audio performance, in terms of signal-to-noise ratio, noise, floor, and distortion, always provide separate analog and digital supplies and grounds. all digital components should be connected to vcc and gnd, directly from the pc bus connectors. single-ended analog circuitry, such as d/a converters, codecs, etc., should be operated from a separate +5v supply which is locally regulated down from the +12v supply available on the pc bus. all operational amplifiers should be powered by filtered 12v supplies derived from the 12v supplies available on the pc bus. operational amplifiers should never be operated from a single-ended supply. this will not only reduce the dynamic range and headroom, but also significantly degrade the signal-to-noise ratio. handling grounds for optimum audio performance, it would be most desirable to keep the analog and digital supplies and returns totally isolated from one another. however, for the sake of emi (fcc) performance, it is generally necessary to keep all supplies closely coupled. also, in a pc, there are a limited number of supplies to work from, and only a single gnd. these conflicting requirements are best met by allowing the digital and analog returns (gnd & agnd) to be directly connected at only a single location, preferably directly adjacent to the card bracket. this single connection should be a substantial one, at least 100-200 mils. this connection is indicated in the evaluation board schematics as a gndstrap component. ac coupling the returns by means of 1-10nf capacitors straddling the perimeter of the agnd/gnd planes, at intervals of no more than 1-1.5 ?, should provide the coupling necessary to prevent emi problems which can be caused by the separate ground planes. the db-15 connector shell must be securely connected to the gnd plane, and the connector must be securely screwed to the bottom of the bracket, while the top of the bracket should have a tab which is securely screwed of riveted to the agnd plane, thus referencing all outgoing signal lines to the (relatively) clean chassis ground at the bracket. in past designs, these techniques have consistently resulted in a > 10db margin relative to the fcc class-b limits. in the analog section, it is desirable to have two agnd planes, rather than a single agnd plane, and a single power plane. all analog supplies can be easily routed as normal traces, since the currents are very low. if possible, place the agnd planes on the outer layer, and do all signal and power routing on the two inner layers, to minimize noise pickup from adjacent boards. in smt designs, make layers 2 & 4 agnd planes, and place as much routing as possible on layer 3, minimizing exposed routing on layer 1. the agnd plane should completely underlie all analog circuitry, including and d/a or a/d converters or codecs. there should be no vcc or gnd routing, or unnecessary digital signal routing through the area covered by the agnd plane. analog signal routing proper component is essential to getting optimum audio performance. all traces should be kept as short and straight as possible. avoid running traces parallel to other traces for other than very short distances. keep any digital or clock traces as far as possible from a/d and d/a converters. to minimize noise pickup, all routing to op-amp inputs should be kept as short as possible. op-amp output signals are far less critical, being driven by a relatively low impedance source. avoid routing op- amp input and output signals near each other to prevent feedback problems. also, be sure to follow the supply bypassing guidelines below. never route an analog signal through a digital area, or vice- versa.
KS0164 multimedia audio 18 / 19 audio board design & pcb layout guidelines(continued) digital signal routing use of vias should be minimized, particularly on high speed signals, such as clocks. for this reason, hand-routing is strongly recommended, rather than using an auto- router. even the auto- routers available today will use far more vias than an experienced hand- router. our evaluation boards are all completely hand-routed. keep all unbuffered pc- bus signals as short as possible, preferably no more than 1-2 ?. also rigorously avoid passing digital signals over any splits in the planes. keep all crystals as close as possible to the other components to which they are connected, and, if possible, surround their traces with gnd traces. never allow an oscillator or clock signal to cross the gnd/agnd plane split! securely attach, by soldering, the crystal case to its associated ground plane, usually gnd. supply bypassing in the digital section of the board, be sure no vcc pin is more than about 1 ? from a bypass capacitor. in the analog section, this may be relaxed somewhat, but try to ensure that each supply pin is within at least 1.5-2 ? of a bypass capacitor. in both the digital and analog sections, evenly distribute the bypass capacitors, and use an even mix of 0.1 m f and 0.001 m f capacitors. for the ks0165, one bypass capacitor for each vcc pin is recommended. all bypass capacitors should be routed such that the connection is from the vcc and gnd planes to the capacitor, and then from the capacitor to the ic pins. emi suppression adequate emi suppression can most easily be achieved through careful pcb layout, and the use of small capacitors to gnd/agnd, rather than ferrite beads. since the analog input and output signal points are all (relatively) low impedance, small capacitors(1-10nf) can be connected between these points and agnd with no appreciable effect on audio performance. all such capacitors should be places as close as possible to the connectors, and the traces leaving them (going to the connectors) should not pass near any unfiltered traces which might couple-in unwanted high-frequency noise.
KS0164 multimedia audio 19 / 19 package dimensions (100-qfp-1420c) #1 0.65 0.30 0.10 (0.58) (0.83) 20.00 0.20 23.90 0.30 #100 14.00 0.20 17.90 0.30 0.80 0.20 2.65 0.10 3.00max 0.00min 0.80 0.20 0 - 8 0.15 +0.10 -0.05 0.10max 0.10max

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